Oscillator synchronization

ABSTRACT

A relaxation oscillator having a natural frequency substantially the same as the frequency of a source of AC power is synchronized from the power source without the use of any DC connection to or from the oscillator. The natural frequency of the oscillator is momentarily depressed just prior to and during the application of synchronizing pulses to the oscillator from the AC source. The arrangement is particularly useful in a standby power supply system which is synchronized to an AC power line at all times and which continues to supply power after the line fails. The standby power supply includes an inverter that is driven at the AC power source frequency by the synchronized oscillator.

United States Patent Rolfes et a1. [4 Mar. 21, 1972 [54] OSCILLATORSYNCHRONIZATION 3,365,651 1/1 968 Rolfes ..321/43 [72] Inventors: PaulE. Rolfes, Costa Mesa, Califi; Robert Primary Examiner john KominskiJameson Guadalajara Mexico Attorney-Gausewitz, Carr & Rothenberg [73]Assignee: Lorain Products Corporation, Lorain,

Ohio [57] ABSTRACT Filedl 1969 A relaxation oscillator having a naturalfrequency substan- [211 Appl No: 885,898 tially thesame as the frequencyof a source of AC power is synchronized from the power source withoutthe use of any DC connection to or from the oscillatorIThe naturalfrequen- U.S. l 1, cy of the oscillator is momentarily depressed justprior to and 331/153 307/269 during the application of synchronizingpulses to the oscillator [51 Ill. C1. ..l'l03k 3/08 from the c sow-caThe arrangement i particularly useful i Fleld of Search a Standby powerpp y system which is synchtonized to an 3 H172 AC power line at alltimes and which continues to supply power after the line fails. Thestandby power supply includes [56] References Cited an inverter that isdriven at the AC power source frequency by UNITED STATES PATENTS thesynchronized oscillator.

3,210,691 10/1965 Sprott ..33 1/145 12 Claims, 4 Drawing Figures d? a 6a I A! Ii OSCILLATOR SYNCHRONIZATION BACKGROUND OF THE INVENTION 1.Field of the Invention This invention relates to synchronization ofoscillators and more particularly concerns a method and apparatus forproviding synchronization of an oscillator without any DC connections.It is frequently necessary to synchronize an inverter to another sourceof AC power such as a second inverter or an AC power line, despite thefact that the inverter to be synchronized has a free running or naturalfrequency equal to or greater than the frequency of the second powersource.

Reference is made, for example, to U.S. Pat. No. 3,348,060 to R. S.Jamieson for a Continuously Operating Standby Power Supply and BatteryCharging Apparatus and Method. In a standby power supply system such asshown and described in this patent, it may be necessary to synchronizethe system to the line while the line is being supplied by a dieselpowered generator during extended period of power failure. Such agenerator may be characterized by a relatively wide frequency swing, asmuch as :3 cycles per second. Therefore, it is necessary to provide anoscillator that may be synchronized from a source that is subject tofrequency variations.

2. Description of the Prior Art An inverter that is driven by arelaxation oscillator, as well known to the art, has generally beensynchronized to a frequency higher than the free running frequency ofthe oscillator and the inverter driven thereby. For this reason, manyprevious systems have not provided an inverter with a free runningfrequency equal to the frequency of the AC source from which asynchronizing signal is to be derived. This, of course, is undesirable,since in the event of a power failure, the load originally driven fromthe AC source will be driven at the lower, natural frequency of theinverter and its driving oscillator.

The problem of insuring that synchronization of the inverter with the ACsource will occur and at the same time maintaining the free runningfrequency of the inverter substantially equal to the synchronizedfrequency is one that has presented substantial difficulties to workersin the art. This problem was v considered and a solution suggested inU.S. Pat. No.v

3,365,651 to Paul E. Rolfes for Apparatus and Method for Synchronizingan Inverter to a Source of AC Power.

In the Rolfes patent, a relaxation oscillator for driving the inverterof a standby power supply is provided with a natural frequency that issubstantially equal to the line frequency or the frequency of the sourceof AC power whereby upon failure of the power source the inverter isdriven at the natural frequency of the relaxation oscillator and theload sees substantially no change in frequency. However, in order toenable synchronization of the inverter and its driving relaxationoscillator from the AC power source even though the frequencies of thetwo are substantially the same, and even though within tolerance limitsthe frequency of the AC power source may drop one or two cycles belowthe frequency of the oscillator, the Rolfes patent derives a steady DCsignal from the AC power source and provides a steady frequencydepressing DC signal to the unijunction transistor of the relaxationoscillator. This DC signal maintains the oscillator frequency at a valuesignificantly lower than its natural frequency whereby synchronizingpulses at the frequency of the AC power source may exactly synchronizethe oscillator to the source frequency. In this system, upon loss of thepower source, the relaxation oscillator goes back to its naturalfrequency and the standby power supply provides power of the desiredfrequency. However, the system of the Rolfes patent suffers from severaldefects. First, if the frequency depressing DC signal were to be lostwithout loss of the synchronizing signal, the system would be subject topossible loss' of synchronization where the AC source frequency is equalto or less than the natural frequency of the oscillator. Alternatively,should the synchronizing signal from the AC source be lost without lossof the DC frequency depress signal then the oscillator frequency isconsiderably depressed.

Still another problem of the system of the Rolfes patent derives fromits requirement of a DC steady state frequency depressing signal. Sinceit is well known that standby systems must retain their operativecapabilities over long periods of time such systems are inordinatelysubject to drift induced by DC connections. Current leakages through DCconnecting devices and in particular diodes, for example, are such as torender stability requirements of this type of circuitry almostimpossible to attain. AC connecting devices such as capacitors, on theother hand, are known to be available in considerably higher quality sothat such components can be selected with considerably less leakage.

SUMMARY OF THE INVENTION In the practice of the present invention inaccordance with a preferred embodiment thereof, an oscillator issynchronized from a train of synchronizing pulses without any DCconnection even though the synchronizing pulses have a repetition rateor frequency substantially equal to the natural frequency of theoscillator. Such synchronization is made possible despite the fact thatthe synchronizing source may be at a slightly lower frequency than theoscillator natural frequency by momentarily depressing the naturalfrequency of the oscillator when the synchronizing pulses are applied.The oscillators natural frequency is depressed for for a time just priorto and during the occurrence of each oscillator synchronizing pulsewhereby despite the fact that the synchronizing pulse source may have afrequency slightly less than the'natural frequency of the oscillator,synchronization can take place.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of asynchronized oscillator built according to principles of this invention,

FIG. 2 illustrates certain timing and wave forms of the synchronizationand frequency depressing method of this invention,

FIG. 3 is a synchrograph showing relative timing of various wave formsof the system, and

FIG. 4 is a block diagram of an inverter power supply system employingthe synchronized oscillator of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Illustrated in FIG. 1 is asubstantially conventional relaxation oscillator comprising a capacitor10 connected at one side thereof to ground or a source of negativevoltage 12 and connected at the other side thereof to a source ofpositive voltage 14 through a charging resistor 16. The junction 18between the capacitor 10 and resistor 16 is connected to the emitterelectrode 20 of a unijunction transistor 22 having a base-two electrode24 connected to the positive supply through a resistor 26 and having abase-one electrode 28 connected to the negative supply via a resistor30.

Many different types and arrangements of relaxation oscillators andother oscillators are well known and a number of these may be employedin a practice of the present invention. However, the circuit illustratedis preferred for convenience of application of the synchronizing anddepressing signals as more particularly described below.

The output of the oscillator, taken at the base-one electrode 28, is fedvia an output capacitor 32 to effect synchronization of an inverter (notshown in this figure). The oscillator output that is fed to the invertercomprises the series of sharp synchronizing or triggering pulses 34.

Since, as previously described, the preferred embodiment of thisinvention is specifically adapted for use with a standby inverter powersupply, it may be assumed that the natural frequency of the oscillatoris desirably 60 Hz., having a period of 8.33 milliseconds. Therefore, asis well known, values of resistor 16 and capacitor 10 are selected toprovide a freerunning or natural period of oscillation of 8.33milliseconds. Resistors 26 and 30 in this oscillator are selected forstability of operation of the unijunction transistor. Although theoutput of the oscillator may be taken at a number of different points,for the purposes of this discussion, it is assumed that the output istaken as indicated at the base-one electrode 28, the junction oftransistor 22 and resistor 30. The output at this point is the positivegoing pulse train 34 at a repetition rate of 8.33 milliseconds in thisexpository embodiment. The inverter, when driven by this pulse train hasthe desired frequency of 60 Hz.

As mentioned above, in order to avoid DC leakage of currents and toobtain maximum stability of oscillation, it is desirable to avoid DC ordirect connections to the oscillator. Since the output is in the form ofpositive going pulses, the output may be capacitively coupled to thenext stage and to the inverter, thus requiring no DC or directconnections to the oscillator by means of its output.

In the following discussion, it will be shown that such a stableoscillator, having no DC connections can be used to drive a powerinverter and can be synchronized to a frequency source that is of thesame frequency or nearly the same frequency or of a somewhat lowerfrequency than the oscillator natural frequency. If the oscillator isexactly the same frequency as the source to which it is to besynchronized but is out of phase with the source, it is impossible toever achieve synchronization. Further, if the oscillator is operating ata frequency incrementally higher than the synchronizing sourcefrequency, it would be impossible to synchronize to the source frequencywith the circuitry described to this point because, with this type ofoscillator the only method of synchronization that can be employed isthat which increases its natural operating frequency. Such asynchronization can be introduced at a number of points in theoscillator circuitry illustrated in FIG. 1. However, for purposes ofthis discussion, it will be considered that synchronization will beperformed by the introduction of a negative going pulse 36 at thejunction of resistor 26 and transistor 22. As is well known with aunijunction transistor, the point at which the transistor fires, thatis, conducts through its emitter to electrode 28, is determined by therelation of the voltage level on the emitter electrode and the voltageon one or both of the base electrodes. For example, with the voltage onthe electrode 28 held at fixed level, the voltage required on theemitter electrode 20 to cause the normally nonconducting transistor toconduct increases with increases in the voltage level on the electrode24. Conversely, as the voltage on electrode 24 is decreased, the voltageon the emitter electrode 20 that is required to fire the transistorconcomitantly decreases. Accordingly, it will be seen that the magnitudeof the negative going synch pulse 36 that is introduced at the junctionof resistor 26 and the transistor will determine the amount that theoscillator frequency can be increased by the synchronizing pulse. Byproper selection of amplitude of this synchronizing pulse, it can bearranged that the oscillator frequency will be increased to the desiredamount and no more. Thus the amplitude of the synchronizing pulse ischosen so that the maximum increase in frequency that may be caused bythis pulse does not exceed selected oscillator frequency tolerances.

Assume for purposes of this description that the inverter (to be drivenby the illustrated relaxation oscillator) frequency must never exceed atolerance of :1 percent. In order to achieve this goal, it will beassumed that the oscillator is stabilized to one-tenth of 1 percent andthe AC source has a stability of iljpercent. For such a situation, thesynch pulse amplitude would be so selected as to cause a maximumincrease of the frequency of the natural oscillator frequency of lpercent. If the AC source frequency, which is preferably the same as thefrequency of synch pulses 36, is higher than the natural frequency ofthe oscillator there is no difficulty in synchronizing the oscillator byfeeding these negative going synchronizing pulses as indicated. The.oscillator natural frequency will then be lower than the synchronizingfrequency and the natural frequency can thus be momentarily increased byapplication of the synchronizing pulse. If, however, the sourcefrequency (the frequency of synchronizing pulses 36) is lower than thenatural frequency of the oscillator, it will be readily understood thatthe oscillator will have completed one full cycle, that is, theunijunction 22 will have fired, before the synch pulse occurs; andtherefore, the synch pulses 36 will have no effect.

For such a condition, where the source or synch frequency is lower thanthe natural frequency of the oscillator, it is necessary to decrease thefrequency of the oscillator in such a manner as to avoid exceeding thetolerance limits of :1 percent of the natural frequency under anycircumstance.

The oscillator frequency can be decreased by increasing the voltage atthe junction of resistor 26 and the transistor 22. Therefore, if thispoint is raised in voltage for a very short duration of time, for a timeimmediately prior to the application of the synch pulse 36, it ispossible to synchronize the oscillator to a frequency that is lower thanits natural frequency. Furthermore, having the requirement only todecrease or depress the oscillator natural frequency for a relativelyshort period of time, there is no need for DC connections and thefrequency depressing circuitry can be AC coupled to the oscillator.

Frequency depressing is provided by a circuit including an NPNtransistor 38 having its emitter connected to the negative supplyvoltage and having its collector connected by-a resistive voltagedivider comprising resistors 40 and 42 to the positive supply. To thejunction of the resistors 40 and 42, there is connected the anode of adiode 44 which has its cathode connected via a capacitor 46 to thejunction of resistor 26 and transistor 22. A train of negative goingsubstantially square wave frequency depressing pulses 48 is coupled tothe base of transistor 38 through a coupling capacitor 50, a Zener diode52, and across a resistor 54 that is connected between the negativesource of potential and the junction of the base of the transistor 38with the anode of Zener diode 52. A resistor 56, connected between theZener diode cathode and the positive supply provides bias for thecircuit.

As illustrated in FIG. 1, the transistor 38 is normally held in the onposition, that is, conducting heavily by the relatively high level ofvoltage provided via resistor 56 from the positive voltage source. Inthis manner, the cathode of the Zener diode 52 is held at a relativelyhigh potential whereby the transistor 38 will conduct. Conduction of thetransistor 38 provides a relatively low potential on the anode of diode44 with respect to its cathode whereby this diode is cut off. Uponoccurrence of a depress pulse 48,'a negative going signal is fed acrossthe capacitor 50 to the cathode of diode 52 and to provide a negativegoing signal to the base of transistor 38 which is thereby cut off. Astransistor 38 is cut off, the voltage at the anode of diode 44 rises toprovide through the diode and through capacitor 46 a sharp, positivegoing signal at the junction of resistor 26 and transistor 22. Thiscondition terminates when the depress signal voltage again goes high tocause the cathode of diode 52 to again be raised and to cause transistor38 to again conduct.

For consideration of the effect of the depress pulses 48 upon thefrequency of the relaxation oscillator, reference is made to the graphof FIG. 2. In a normal sequence of operations starting from a time t theoscillator providing the desired 60 cycle synchronization of an inverterwill have a natural period of 833 milliseconds. However, if at a time of8 milliseconds after time t at a time indicated at t, in FIG. 2, thevoltage at the depress point is lowered, the frequency of the oscillatoris shifted downward. If at subsequent time t; that occurs at the end ofan additional 0.4] milliseconds, a total of 8.41 milliseconds from t thevoltage at the depress pulse is allowed to again go high, the oscillatorwill again return to its normal free-running mode. In FIG. 2, the pulse58 that occurs in the time interval between t, and t, represents theincrease of voltage at the junction of resistor 26 and transistor 22 inFIG. 1 and the line 60 represents an idealistically linear chargingvoltage on the capacitor 10 which is, of course, the voltage at theemitter 20 of the unijunction transistor 22. Considering the voltagelevel indicated at 62 in FIG. 2 to be the voltage normally provided atelectrode 24 of the transistor, it is assumed that the transistor willnormally fire at time 1 the point at which the voltage 60 on thetransistor emitter reaches a point where it is equal to the voltagelevel 62. It will be understood that the equality or coincidence betweenthe voltage level 64 on the transistor emitter and the voltage level 62on the transistor electrode 24 is not a necessary concomitant ofoperation of this transistor since the transistor operates not uponequality of these voltages necessarily, but upon the occurrence of apredetermined relation therebetween.

It will be seen that if at time t, the voltage on the electrode 24 israised, as by the occurrence of the pulse 58, the transistor will notfire at time but rather the voltage of the emitter electrode willcontinue to rise. If now, at time the pulse 58 terminates and thedepress signal is removed, electrode 24 immediately returns to itsnormal voltage state, and the oscillator would immediately fire at suchtime If the pulse width from t, to I is so chosen and the time ofinitiation of such pulse I is chosen such that the time t occurs at 8.41milliseconds after the initiation of the oscillator cycle, it will beseen that the use of this depress control circuitry cannot possiblydepress the oscillator frequency beyond the I percent frequencytolerance. In other words in order to retain operation within apreselected tolerance, it is necessary only to initiate the depress at atime t, sufficiently early to prevent triggering by a synch pulse thathas been increased in frequency within the tolerance limits of thesynchronization source and then to insure termination of the depresspulse at a time after occurrence of the termination of the naturaloscillator period that is not greater than the maximum tolerabledecrease of oscillator frequency. In other words, if synch pulses areabsent, the oscillator will still fire at the termination of the depresspulse, and will still remain within tolerance limits.

Having described the method of depressing the oscillator frequency, themethod and apparatus for synchronization of the oscillator to thefrequency of the AC source which in this example also has a half periodof 8.3 milliseconds will now be described.

Starting at time t as indicated in FIG. 2, capacitor begins to chargeand the oscillator period begins. The oscillator would normally fire att 8.33 milliseconds after t but the depress signal is introduced at t,,8.00 milliseconds after t and thus prevents the oscillator from firing.The synch signal comprising a number of positive going pulses 66, FIG.1, is provided via a coupling capacitor 68 to the cathode of a Zenerdiode 70 and thence to the base of an NPN transistor 72. The latter isbiased to be normally in the nonconducting condition whereby thepositive going synch pulses applied to its base cause the transistor toconduct through resistor 42, diode 44, and resistor 74 whereupon anegative going pulse 36 is transferred through the capacitor 46 to thejunction of resistor 26 and transistor electrode 24. The momentaryreduction in the voltage on electrode 24 of transistor 22 has the effectof increasing the natural frequency of the oscillator and causes it tofire at that exact time.

Referring to FIG. 2, the synch pulses 66 are caused to occur at time atime which occurs 8.33 milliseconds following time t in the illustratedexample of this embodiment.

By the methods and apparatus illustrated in FIGS. 1 and 2, it will beseen that an oscillator of a precise natural frequency can besynchronized to an AC source of a substantially similar frequencywithout any direct coupling of any signals into or out of theoscillator. All signals are coupled through capacitors thereby allowingfor maximum oscillator stability and minimizing the possibility of DCleakage current and concomitant drift.

Illustrated in FIG. 4 is a standby power supply system employing thefrequency synchronized oscillator described above. Also illustrated inthis figure are the requirements and arrangement for providing thesynchronizing and frequency depressing pulse trains. An inverter 76which may be of the type illustrated in the aforementioned U.S. Pat. toJamieson, No. 3,348,060, comprising a parallel square wave SCR inverterof the type described on page 152 et seq. of the General Electric SCRManual, Second Edition, is provided with a DC power supply 78 that alsoprovides the power to an oscillator 80 of the type illustrated inFIG. 1. The source of AC power 82 is provided to supply power to a load(not shown) and also to the inverter 76. Power may be supplied from thesource of AC power to the inverter by means more particularly describedin the aforesaid .Iamieson U.S. Pat. No. 3,348,060. In such a systemduring normal operations, the AC line is feeding the power to a batterycharger (not shown) which converts the power to DC and supplies such DCpower to the inverter and also to the battery 78 if it should needrecharging. In such a system, the inverter system converts thisDC powerback into AC power and feeds the load. Thus during normal operation, thepower from the AC utility line is being continually converted to DC by acharger and reconverted to AC by the inverter before it is fed to theload. In the event of an AC input power failure, the charger orrectifier simply ceases to function and the inverter receives its inputpower from its battery. During such utility line outages, as long as thebattery voltage remains above a certain preset limit, the inverter willcontinue to supply AC power to the load without interruption.

In FIG. 4 only so'much of the above described system is shown as willprovide the necessary frequency synchronization of the oscillator 80that triggers inverter 76. A pulse forming circuit 84 of a conventionaltype such as for example, one of the SCR trigger circuits shown on pages329 and 330 of the General Electric Transistor Manual, published 1964 byGeneral Electric Company, detects zero crossover points of the AC signalfrom the power source 82 and'generates a train of pulses 66 that aresynchronized from the AC line. These pulses are fed to the oscillator 80as more particularly illustrated in connection with FIG. 1. Thesesynchronizing pulses also identify the start time t for each cycle ofthe oscillator. In addition to synchronizing the oscillator, the synchpulses 66 initiate operation of a first monostable multivibrator oroneshot 86 which is set to provide a pulse 88 that defines a time periodof 8.00 milliseconds, from time t to time t as illustrated in FIG. 3. Atthe end of the period of the one-shot 86, its negative output rises tothereupon trigger a second monostable multivibrator or one-shot 90 whichprovides the negative going depress pulses 48. The period of this secondone-shot 90, which is initiated at time t, and terminates at is exactly0.41 milliseconds for the described example. Thus synch pulses 66,generated at intervals of 8.33 milliseconds, trigger one-shot 86 whichhas an output that lasts for 8.00 milliseconds and thereupon in turntriggers one-shot 90 having a duration of 0.41 milliseconds. From theprevious discussion it will be seen that the times of 8.00 millisecondsand 0.41 milliseconds for the delay periods of the one-shots 86 and 90are selected to maintain a total frequency shift of not more than 1percent of the predetermined 8.33 millisecond natural period of theoscillator. Since the synch pulses 66 occur during the existence of thenegative going depress pulse 48 from the second one-shot 90 therelaxation oscillator is able to be triggered exactly at the time ofoccurrence of such synch pulses. Therefore, the oscillator operates witha time period of exactly 8.33 milliseconds and is precisely synchronizedwith the frequency source.

Specific circuitry of the monostable multivibrators is not describedsince many common forms of such one-shot circuits are available and maybe employed in the practice of this invention. Although multivibratorsare shown and conveniently employed for timing purposes, it will bereadily appreciated that extreme precision methods for determination ofthis timing and similar wave shapes may employ various well-knowndigital methods of counting down from high frequency standard crystalclocks.

From the above description, it will be seen that there has been providedan effective method and apparatus for synchronizing a power inverter ofprecise frequency from a power source of a similar frequency. This hasbeen accomplished while maintaining a frequency stability that does notdepart by more than 1 e'hi' from its normal operating frequency, whichhas been assumed for the purposes of thisdiscussion to be 60 Hz.

Operation of the described circuit under different conditions of failurewill now be described assuming the system to be employed in a commercialpower line and there occurs a failure of a source of AC power. For afailure of the frequency source, a commercial power failure, pulsesformed by the pulse forming circuits 84 would immediately cease to'exist since there is no AC input to generate these pulses. Therefore,the synch pulses to the oscillator disappear and the oscillator nowoperates in its unsynchronized mode.- Monostable multivibrator or oneshot 86, however, will have already been set by the previoussynchronization pulse, that pulse being the last pulse that occurredprior to the power failure, and would be in the process of timing outits 8 millisecond period. At the end of this time, it triggers thesecond one shot 90 which momentarily depresses the oscillator frequencyfor an additional period of 0.41 milliseconds. Therefore, since thesynch pulse no longer exists, the oscillator will not be fired by thesynch pulse and will fire in this situation only at the end of theadditional 0.41 millisecond delay of the second one shot 90. This causesthe first oscillator cycle that occurs after line failure to be extendedin time to a total time of 8.41 milliseconds rather than the normal 8.33milliseconds and provides for an increase of the period of 1 percent. Itcan be seen then, that by selection of time in the monostablemultivibrator or by proper selection of wave shapes as derived from aclock or other means of selection of the depress pulse widths, it ispossible to achieve a system that will never exceed the stated frequencytolerance by decreasing its natural frequency by more than 1 percent. Itis noted that the natural frequency cannot be increased in the case offailure of the power source since the oscillator will then continue tooperate at its natural frequency.

In the event of failure of the synch pulses, that is if they are notavailable to the oscillator, the first cycle of the oscillator againwould be the extended period of 8.41 milliseconds, the same as wouldoccur with a failure of the frequency source. However, since the failurewould occur only in the synchronizing signal itself, in this particularexample, the pulse forming circuits would still be triggering the oneshot 86 and, in turn,

' the one shot 90. The oscillator in such a situation would continue tooperate with a period of 8.33 milliseconds after the first cycle sincethe start time of each cycle is now coincident with the termination ofthe depress pulse 48 and the period between the trailing edge ofsucceeding ones of these depress pulses is still 8.33 milliseconds. Thiswould result in a continuation of the inverter operation essentially insynchronization with the source of AC power. There would, however, inthis situation occur a slight phase displacement of 0.08 millisecondsdue to the extension of the first cycle after loss of synchronizationpulse.

Consider now the operation of the circuit that would take place withfailure of one of the one-shot multivibrators. The oscillator, in suchan occurrence, would return to its normal free-running mode since thesignals from the second one-shot monostable multivibrator 90 arecapacitively coupled to the oscillator after the first operation of thisone-shot. If the latter should fail to operate regardless of which oneof its states the failure occurred in, the oscillator continues tooperate in its normal manner since there is no DC connection from theone shot to the oscillator. The effect is merely to lose the frequencydepress signal. Therefore, if the oscillator happens to be operating ina frequency that is slightly faster than the AC source, the oscillatorwould merely continue on in its freerunning mode. If the oscillatorhappened to be operating at a frequency that was slightly lower than theAC source with a failure of the one shots, the oscillator would continueto operate in synchronization since it would still receive thesynchronizing pulses 66 from the pulse forming circuit 84. In eithercase, however, the oscillator change, if any, would not exceed the totalfrequency tolerance previously determined to be il percent.

There has been described a system for a standby power supply employingan improved method and apparatus for oscillator synchronization whichenables the oscillator and inverter of the power supply to operate witha natural frequency substantially equal to or somewhat greater than themain source of AC power and nevertheless, be synchronized therewith, allwithout employing any DC connections to the oscillator. Thus a system ofgreatly improved stability has been described.

We claim:

1. A method of synchronizing an oscillator having a natural frequencyfrom a signal source of substantially similar frequency comprising thesteps of generating synchronizing pulses from said source, applying saidpulses to synchronize the oscillator, and

momentarily depressing the natural frequency of the oscillator when thesynchronizing pulses are applied, said last mentioned step comprises thestep of applying frequency depressing pulses to the oscillator.

2. The method of claim 1 wherein each said depressing pulse terminatesafter a time interval following a synchronizing pulse that issubstantially equal to the maximum increase of period of the oscillatorthat is within a predetermined allowable tolerance,

whereby the oscillator frequency will be maintained within saidtolerance even in the absence of said synchronizing pulses.

3. In combination an oscillator,

means for applying a train of synchronizing pulses to the oscillator,and

means for momentarily depressing the oscillator frequency just prior toand during each synchronizing pulse, said last mentioned meanscomprising means for capacitively coupling to the oscillator a train offrequency depressing pulses, each said depressing pulse being initiatedat a time immediately preceding each synchronizing pulse that comprisesa minor portion of the period between succeeding synchronizing pulses,and each said depressing pulse having a duration such that is terminatesat a time immediately following each synchronizing pulse that is notgreater than the maximum increase of oscillator period within apredetermined allowable tolerance.

4. The combination of claim 3 wherein said last mentioned meanscomprises means for capacitively coupling to the oscillator a train ofdepressing pulses of predetermined duration.

5. The combination of claim 3 wherein said train of depressing pulses issynchronized with said synchronizing pulses and has a duration such thateach depressing pulse of said train continues for a time after theimmediately preceding synchronizing pulse that is not greater than themaximum increase of period of the oscillator that is within apredetermined allowable tolerance,

whereby the oscillator frequency will be maintained within saidtolerance even in the absence of said synchronizing pulses.

6. The combination of claim 5 wherein the oscillator comprises a seriesconnected resistor and capacitor and a switching device,

said switching device having first and second input electrodes and anoutput electrode, and being connected to provide an output when signalsat its input electrodes bear a predetermined relation to each other,

said first input electrode being connected to the junction of saidresistor and capacitor, and

means for coupling said trains of synchronizing and depressing pulses tosaid second input electrode.

7. The combination of claim 6 wherein said means for coupling said trainof depressing pulses to said second input electrode comprises a diode,

a potential source,

a resistor coupled between one side of the diode and one side of thepotential source,

a first transistor having a collector electrode resistively connected tothe cathode of the diode, having an emitter electrode connected to theother side of the potential source, and having a base electrode, a Zenerdiode having one side thereof connected to said base electrode,

a coupling capacitor having one side thereof connected to the other sideof the Zener diode and having the other side thereof adapted to receivesaid train of depressing pulses, and

a second coupling capacitor connected between the other side of thefirst mentioned diode and the second input electrode of said switchingdevice.

8,v The combination of claim 7 wherein said means for coupling saidtrain of synchronizing pulses includes said first mentioned diode andsaid second coupling capacitor, and further includes a second transistorhaving a collector electrode resistively coupled to said one side ofsaid first mentioned diode, having an emitter electrode connected tosaid other side of said potential source, and having a base electrode, asecond Zener diode having one side thereof connected to the base of thesecond transistor, and

a third coupling capacitor having one side thereof connected to theother side of said second Zener diode and the other side thereofconnected to receive said train of synchronizing pulses.

9. A power supply comprising a source of AC power,

an inverter,

a source of DC power for the inverter,

an oscillator for supplying trigger signals to the inverter and having afrequency substantially similar to the frequency of the AC source,

means for synchronizing the oscillator from the AC source,

means for momentarily depressing the frequency of the oscillator justbefore each synchronization thereof, and

means for blocking flow of DC current to and from the oscillator andeither of said AC source and said inverter, said means for momentarilydepressing frequency comprising means for applying to the oscillator atrain of frequency depressing pulses, each of said depressing pulsesbeing initiated prior to synchronization of the oscillator from the ACsource and terminating after a time interval following thesynchronization of the oscillator that is substantially equal to themaximum increase of period of the oscillator that is within apredetermined allowable tolerance.

10. The combination of claim 9 wherein the oscillator comprises a seriesconnected resistor and capacitor and a switching device,

said switching device having first and second input electrodes and anoutput electrode, and being connected to provide an output when signalsat its input electrodes bear a predetermined relation to each other,

said first input electrode being connected to the junction of saidresistor and capacitor, and

said means for momentarily depressing the frequency of the oscillatorcomprising a first delay device having a triggering input from said ACsource,

a second delay device having a triggering input from the first delaydevice and providing a frequency depressing output pulse, and

a second switching device capacitively coupled to the said second inputelectrode and having an input capacitively coupled to the depressingoutput pulses from said second delay device.

11. The combination of claim 10 including a pulse forming networkresponsive to and synchronized from said AC source,

said means for synchronizing the oscillator comprising a third switchindevice capacitively connected to said second input e ectrode of thefirst mentioned switching device and having an input capacitivelycoupled to said pulse forming network,

said first mentioned delay device having a triggering input from saidpulse forming network.

12. The combination of claim 11 including a diode connected in commonbetween said second input electrode of the first mentioned switchingdevice and both of said second and third switching devices.

UNITED STATES PATENT oTEIEE CERTEFEATE OF QQRREfiTION Dated March 21,1972 Patent No. 3,651,427

Inventor(s) Paul E. Rolfes and Robert 80 Jamieson It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

Claim 3, line 15, change "is" to -=-=-it===o Signed and sealed this 19thday of September 19 72.

(SEAL) Attest:

EDWARD M.FLETCI-ER,JR ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents fi U.S. GOVERNMENT PRINTING OFFICE: 19.9 0"366384 FORMPO-1050 (O-69)

1. A method of synchronizing an oscillator having a natural frequencyfrom a signal source of substantially similar frequency comprising thesteps of generating synchronizing pulses from said source, applying saidpulses to synchronize the oscillator, and momentarily depressing thenatural frequency of the oscillator when the synchronizing pulses areapplied, said last mentioned step comprises the step of applyingfrequency depressing pulses to the oscillator.
 2. The method of claim 1wherein each said depressing pulse terminates after a time intervalfollowing a synchronizing pulse that is substantially equal to themaximum increase of period of the oscillator that is within apredetermined allowable tolerance, whereby the oscillator frequency willbe maintained within said tolerance even in the absence of saidsynchronizing pulses.
 3. In combination an oscillator, means forapplying a train of synchronizing pulses to the oscillator, and meansfor momentarily depressing the oscillator frequency just prior to andduring each synchronizing pulse, said last mentioned means comprisingmeans for capacitively coupling to the oscillator a train of frequencydepressing pulses, each said depressing pulse being initiated at a timeimmediately preceding each synchronizing pulse that comprises a minorportion of the period between succeeding synchronizing pulses, and eachsaid depressing pulse having a duration such that is terminates at atime immediately following each synchronizing pulse that is not greaterthan the maximum increase of oscillator period within a predeterminedallowable tolerance.
 4. The combination of claim 3 wherein said lastmentioned means comprises means for capacitively coupling to theoscillator a train of depressing pulses of predetermined duration. 5.The combination of claim 3 wherein said train of depressing pulses issynchronized with said synchronizing pulses and has a duration such thateach depressing pulse of said train continues for a time after theimmediately preceding synchronizing pulse that is not greater than themaximum increase of period of the oscillator that is within apredetermined allowable tolerance, whereby the oscillator frequency willbe maintained within said tolerance even in the absence of saidsynchronizing pulses.
 6. The combination of claim 5 wherein theoscillator comprises a series connected resistor and capacitor and aswitching device, said switching device having first and second inputelectrodes and an output electrode, and being connected to provide anoutput when signals at its input electrodes bear a predeterminedrelation to each other, said first input electrode being connected tothe junction of said resistor and capacitor, and means for coupling saidtrains of synchronizing and depressing pulses to said second inputelectrode.
 7. The combination of claim 6 wherein said means for couplingsaid train of depressing pulses to said second input electrode comprisesa diode, a potential source, a resistor coupled between one side of thediode and one side of the potential source, a first transistor having acollector electrode resistively connected to the cathode of the diode,having an emitter electrode connected to the other side of the potentialsource, and having a base electrode, a Zener diode having one sidethereof cOnnected to said base electrode, a coupling capacitor havingone side thereof connected to the other side of the Zener diode andhaving the other side thereof adapted to receive said train ofdepressing pulses, and a second coupling capacitor connected between theother side of the first mentioned diode and the second input electrodeof said switching device.
 8. The combination of claim 7 wherein saidmeans for coupling said train of synchronizing pulses includes saidfirst mentioned diode and said second coupling capacitor, and furtherincludes a second transistor having a collector electrode resistivelycoupled to said one side of said first mentioned diode, having anemitter electrode connected to said other side of said potential source,and having a base electrode, a second Zener diode having one sidethereof connected to the base of the second transistor, and a thirdcoupling capacitor having one side thereof connected to the other sideof said second Zener diode and the other side thereof connected toreceive said train of synchronizing pulses.
 9. A power supply comprisinga source of AC power, an inverter, a source of DC power for theinverter, an oscillator for supplying trigger signals to the inverterand having a frequency substantially similar to the frequency of the ACsource, means for synchronizing the oscillator from the AC source, meansfor momentarily depressing the frequency of the oscillator just beforeeach synchronization thereof, and means for blocking flow of DC currentto and from the oscillator and either of said AC source and saidinverter, said means for momentarily depressing frequency comprisingmeans for applying to the oscillator a train of frequency depressingpulses, each of said depressing pulses being initiated prior tosynchronization of the oscillator from the AC source and terminatingafter a time interval following the synchronization of the oscillatorthat is substantially equal to the maximum increase of period of theoscillator that is within a predetermined allowable tolerance.
 10. Thecombination of claim 9 wherein the oscillator comprises a seriesconnected resistor and capacitor and a switching device, said switchingdevice having first and second input electrodes and an output electrode,and being connected to provide an output when signals at its inputelectrodes bear a predetermined relation to each other, said first inputelectrode being connected to the junction of said resistor andcapacitor, and said means for momentarily depressing the frequency ofthe oscillator comprising a first delay device having a triggering inputfrom said AC source, a second delay device having a triggering inputfrom the first delay device and providing a frequency depressing outputpulse, and a second switching device capacitively coupled to the saidsecond input electrode and having an input capacitively coupled to thedepressing output pulses from said second delay device.
 11. Thecombination of claim 10 including a pulse forming network responsive toand synchronized from said AC source, said means for synchronizing theoscillator comprising a third switching device capacitively connected tosaid second input electrode of the first mentioned switching device andhaving an input capacitively coupled to said pulse forming network, saidfirst mentioned delay device having a triggering input from said pulseforming network.
 12. The combination of claim 11 including a diodeconnected in common between said second input electrode of the firstmentioned switching device and both of said second and third switchingdevices.